The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same. More particularly, the invention relates to a semiconductor integrated circuit device comprising an SRAM (static random access memory). A general description of the SRAM is found illustratively in IEDM (International Electron Device Meeting), Tech. Dig., pp. 477-480, 1991.
As a semiconductor memory, the SRAM comprises memory cells each composed of a flip-flop circuit and two transfer MISFETs (metal insulator semiconductor field effect transistors) at an intersection formed by complementary data lines and word lines.
Each transfer MISFET constituting part of a memory cell has one of its semiconductor regions connected to the I/O terminals of the flip-flop circuit; the other semiconductor region is connected to one complementary data line. The word lines, connected to the gate electrodes of the transfer MISFETs, control the conduction thereof.
The flip-flop circuit of each memory cell is constituted as a data retaining unit made of two driver MISFETs and two load resistance elements. Each driver MISFET has one of its semiconductor regions (drain) connected to one semiconductor region of one transfer MISFET; the other semiconductor region (source) of the driver MISFET is connected to a reference voltage line. The gate electrode of the driver MISFET is connected to the other semiconductor region of the transfer MISFET.
One end of each load resistance element is connected to one semiconductor region of each transfer MISFET. The other end of the load resistance elements is connected to supply voltage lines. The load resistance elements are deposited in layered fashion on top of the driver MISFETs in order to reduce the memory cell area for higher integration.
Recent years have seen SRAMs of the above-described type further integrated to accommodate large amounts of data and to operate at high speeds. This type of SRAM is described illustratively in U.S. Pat. No. 5,239,196 (U.S. Ser. No. 653,493), assigned to the assignee of the present application on Feb. 11, 1991 with the United States Patent and Trademark Office.
The technology disclosed in the above document primarily involves forming in each memory cell the gate electrodes of the driver MISFETs and those of the transfer MISFETs (word lines) using different conductive strips. The drive and transfer MISFETs intersect with one another in their gate length direction. The word lines extend in the gate length direction of the gate electrodes of the driver MISFETs, and intersect with part of these gate electrodes.
According to the prior art above, part of the driver MISFETs is made to overlap with part of the word lines. The structure reduces the memory cell area, in the gate width direction of the driver MISFETs, by the amount equivalent to the overlapping region. Thus the degree of integration of the SRAM is enhanced.
The above technology also involves connecting in each memory cell a first word line to the gate electrode of a first transfer MISFET while connecting a second word line to the gate electrode of a second transfer MISFET, the second word line being separated from the first word line and extending in the same direction of the latter. Between the first and the second word lines are a first and a second driver MISFET. The first driver MISFET has its drain region connected to one semiconductor region of the first transfer MISFET. The second driver MISFET has its drain region connected to one semiconductor region of the second transfer MISFET. The plane shape of the first transfer and driver MISFETs and that of the second transfer and driver MISFETs are arranged to be symmetrical around the center point of each memory cell. The gate width size of the first and the second transfer MISFETs is made smaller than that of the first and the second driver MISFETs.
The above-described construction inside the memory cell allows for greater margins of alignment in photolithography between the first and the second transfer MISFETs as well as between the first and the second driver MISFETs. The construction contributes to reducing size disparities among the memory elements while ensuring stable memory cell operation. With each memory element reduced in size, the memory cell area is reduced and the SRAM is boosted in terms of integration.
The above technology makes it possible to determine uniquely the separation inside each memory cell between the first transfer MISFET and first driver MISFET on the one hand, and the second transfer MISFET and second driver MISFET on the other. The separation is so determined on the basis of the size of an element-separating region between the first and the second driver MISFETs. Because the unnecessary size (i.e., an empty region equivalent to the clearance between the driver and the transfer MISFETs) is eliminated from the size of the separation, the memory cell size is reduced and the degree of integration of the SRAM is enhanced.
Furthermore, the above technology involves connecting two word lines to the gate electrodes of the two transfer MISFETs in each memory cell. This constitution eliminates the need to wind around the word line (i.e., one word line per memory cell) inside the memory cell to connect the gate electrodes of the two transfer MISFETs. With the two word lines extending over a short distance in a substantially linear manner, the resistance values of the word lines are lowered. This translates into higher speeds at which to write and read data to and from each memory cell, which results in higher operation speeds of the SRAM.
The above technology adopts the so-called complete CMOS (complementary metal oxide semiconductor) structure. The structure involves forming the flip-flop circuit of each memory cell from two driver MISFETs and two load MISFETs in order to lower the standby current. The load MISFETs are deposited in layered fashion on the driver MISFETs to reduce the memory cell area while improving the degree of integration.